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K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 1 - september 2001 document title 256kx16 bit high speed static ram(3.3v operating). operated at commercial and industrial temperature ranges. revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. rev no. rev. 0.0 rev. 1.0 rev. 2.0 rev. 3.0 rev. 4.0 rev. 5.0 remark preliminary preliminary preliminary final final final history initial release with preliminary. 1.1 removed low power version. 1.2 removed data retention characteristics. 1.3 changed i sb1 to 20ma relax d.c parameters. 3.1 delete preliminary 3.2 update d.c parameters and 10ns part. add low power-ver. delete 20ns speed bin item previous current i cc 12ns 180ma 200ma 15ns 175ma 195ma 20ns 170ma 190ma previous current i cc i sb i sb1 i cc i sb i sb1 10ns - 70ma 20ma 160ma 60ma 10ma 12ns 200ma 150ma 15ns 195ma 140ma 20ns 190ma 130ma draft data feb. 12. 1999 mar. 29. 1999 aug. 19. 1999 mar. 27. 2000 apr. 24. 2000 sep. 24. 2001
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 2 - september 2001 256k x 16 bit high-speed cmos static ram the K6R4016V1C is a 4,194,304-bit high-speed static random access memory organized as 262,144 words by 16 bits. the K6R4016V1C uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. also it allows that lower and upper byte access by data byte control( ub , lb ). the device is fabri- cated using samsung s advanced cmos process and designed for high-speed circuit technology. it is particularly well suited for use in high-density high-speed system applications. the K6R4016V1C is packaged in a 400mil 44-pin plastic soj or tsop(ii) forward or 48 fine pitch bga. general description features ? fast access time 10,12,15ns(max.) ? low power dissipation standby (ttl) : 60ma(max.) (cmos) : 10ma(max.) 1.2ma(max.) l-ver. only operating K6R4016V1C-10 : 160ma(max.) K6R4016V1C-12 : 150ma(max.) K6R4016V1C-15 : 140ma(max.) ? single 3.3 0.3v power supply ? ttl compatible inputs and outputs ? fully static operation - no clock or refresh required ? three state outputs ? 2v minimum data retention : l-ver. only ? center power/ground pin configuration ? data byte control : lb : i/o1~ i/o8, ub : i/o9~ i/o16 ? standard pin configuration K6R4016V1C-j : 44-soj-400 K6R4016V1C-t : 44-tsop2-400bf K6R4016V1C-f : 48-fine pitch bga with 0.75 ball pitch K6R4016V1C-c10/c12/c15 commercial temp. K6R4016V1C-i10/i12/i15 industrial temp. ordering information clk gen. i/o 1 ~i/o 8 oe ub cs functional block diagram r o w s e l e c t data cont. column select clk gen. pre-charge circuit memory array 1024 rows 256 x 16 columns i/o circuit & i/o 9 ~i/o 16 data cont. we lb a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 3 - september 2001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 0 a 1 a 2 a 3 a 4 cs i/o 1 i/o 2 i/o 3 i/o 4 vcc vss i/o 5 i/o 6 i/o 7 i/o 8 we a 5 a 6 a 7 a 8 a 9 pin configuration (top view) soj/ a 17 a 16 a 15 oe ub lb i/o 16 i/o 15 i/o 14 i/o 13 vss vcc i/o 12 i/o 11 i/o 10 i/o 9 n.c a 14 a 13 a 12 a 11 a 10 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 tsop2 lb oe a0 a1 a2 n.c i/o1 ub a3 a4 cs i/o9 i/o2 i/o3 a5 a6 i/o11 i/o10 vss i/o4 a17 a7 i/o12 vcc vcc i/o5 n.c a16 i/o13 vss i/o7 i/o6 a14 a15 i/o14 i/o15 i/o8 n.c a12 a13 we i/o16 n.c a8 a9 a10 a11 n.c 1 2 3 4 5 6 a b c d e f g h 48-csp absolute maximum ratings* * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to 4.6 v voltage on v cc supply relative to v ss v cc -0.5 to 4.6 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature commercial t a 0 to 70 c industrial t a -40 to 85 c pin function pin name pin function a 0 - a 17 address inputs we write enable cs chip select oe output enable lb lower-byte control(i/o 1 ~i/o 8 ) ub upper-byte control(i/o 9 ~i/o 16 ) i/o 1 ~ i/o 16 data inputs/outputs v cc power(+3.3v) v ss ground n.c no connection
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 4 - september 2001 recommended dc operating conditions* (t a =0 to 70 c) * the above parameters are also guaranteed at industrial temperature range. ** v il (min) = -2.0v a.c(pulse width 8ns) for i 20ma . *** v ih (max) = v cc + 2.0v a.c (pulse width 8ns) for i 20ma. parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v ground v ss 0 0 0 v input high voltage v ih 2.0 - v cc +0.3*** v input low voltage v il -0.3** - 0.8 v dc and operating characteristics* (t a =0 to 70 c, vcc= 3.3 0.3v, unless otherwise specified) * the above parameters are also guaranteed at industrial temperature range. parameter symbol test conditions min max unit input leakage current i li v in =v ss to v cc -2 2 m a output leakage current i lo cs =v ih or oe =v ih or we =v il v out = v ss to v cc -2 2 m a operating current i cc min. cycle, 100% duty cs =v il, v in =v ih or v il, i out =0ma com. 10ns - 160 ma 12ns - 150 15ns - 140 ind. 10ns - 175 12ns - 165 15ns - 155 standby current i sb min. cycle, cs =v ih - 60 ma i sb1 f=0mhz, cs 3 v cc -0.2v, v in 3 v cc -0.2v or v in 0.2v normal - 10 l-ver - 1.2 output low voltage level v ol i ol =8ma - 0.4 v output high voltage level v oh i oh =-4ma 2.4 - v capacitance* (t a =25 c, f=1.0mhz) * capacitance is sampled and not 100% tested. item symbol test conditions min max unit input/output capacitance c i/o v i/o =0v - 8 pf input capacitance c in v in =0v - 7 pf
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 5 - september 2001 test conditions* * the above test conditions are also applied at industrial temperature range. parameter value input pulse levels 0v to 3v input rise and fall times 3ns input and output timing reference levels 1.5v output loads see below ac characteristics (t a =0 to 70 c, v cc =3.3 0.3v, unless otherwise noted.) output loads(b) d out 5pf* 319 w 353 w for t hz , t lz , t whz , t ow , t olz & t ohz +3.3v * including scope and jig capacitance output loads(a) d out r l = 50 w z o = 50 w v l = 1.5v 30pf* * capacitive load consists of all components of the test environment. read cycle* * the above parameters are also guaranteed at industrial temperature range. parameter symbol K6R4016V1C-10 K6R4016V1C-12 K6R4016V1C-15 unit min max min max min max read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip select to output t co - 10 - 12 - 15 ns output enable to valid output t oe - 5 - 6 - 7 ns ub , lb access time t ba - 5 - 6 - 7 ns chip enable to low-z output t lz 3 - 3 - 3 - ns output enable to low-z output t olz 0 - 0 - 0 - ns ub , lb enable to low-z output t blz 0 - 0 - 0 - ns chip disable to high-z output t hz 0 5 0 6 0 7 ns output disable to high-z output t ohz 0 5 0 6 0 7 ns ub , lb disable to high-z output t bhz 0 5 0 6 0 7 ns output hold from address change t oh 3 - 3 - 3 - ns
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 6 - september 2001 write cycle* * the above parameters are also guaranteed at industrial temperature range. parameter symbol K6R4016V1C-10 K6R4016V1C-12 K6R4016V1C-15 unit min max min max min max write cycle time t wc 10 - 12 - 15 - ns chip select to end of write t cw 7 - 8 - 10 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 7 - 8 - 10 - ns write pulse width( oe high) t wp 7 - 8 - 10 - ns write pulse width( oe low) t wp1 10 - 12 - 15 - ns ub , lb valid to end of write t bw 7 - 8 - 10 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 5 0 6 0 7 ns data to write time overlap t dw 5 - 6 - 7 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 3 - 3 - 3 - ns address data out previous valid data valid data timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih , ub , lb =v il ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) valid data high-z t rc cs address ub , lb oe data out t hz(3,4,5) t aa t co t ba t oe t olz t lz(4,5) t oh t ohz t bhz(3,4,5) t blz(4,5)
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 7 - september 2001 notes (read cycle) 1. we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs =v il. 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. timing waveform of write cycle(1) ( oe clock) address cs ub , lb we data in data out t wc t cw(3) t bw t wp(2) t as(4) t dh t dw t ohz(6) high-z high-z valid data oe t aw t wr(5) timing waveform of write cycle(2) ( oe =low fixed) address cs ub , lb we data in data out t wc t cw(3) t bw t wp1(2) t dh t dw t wr(5) t as(4) t ow t whz(6) (10) (9) high-z valid data t aw high-z
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 8 - september 2001 notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low cs , we , lb and ub . a write begins at the latest transition cs going low and we going low ; a write ends at the earliest transition cs going high or we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not . be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. if cs goes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. address cs valid data ub , lb we data in data out timing waveform of write cycle(4) ( ub , lb controlled) t wc t cw(3) t bw t wp(2) t dh t dw t wr(5) t aw t as(4) high-z high-z(8) t blz t whz(6) high-z timing waveform of write cycle(3) ( cs =controlled) address cs t aw t dw t dh valid data we data in data out high-z high-z(8) ub , lb t cw(3) t wp(2) t as(4) t wc t wr(5) high-z high-z t lz t whz(6) t bw
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 9 - september 2001 functional description * x means don t care. cs we oe lb ub mode i/o pin supply current i/o 1 ~i/o 8 i/o 9 ~i/o 16 h x x* x x not select high-z high-z i sb , i sb1 l h h x x output disable high-z high-z i cc l x x h h l h l l h read d out high-z i cc h l high-z d out l l d out d out l l x l h write d in high-z i cc h l high-z d in l l d in d in data retention characteristics* (t a =0 to 70 c) * the above parameters are also guaranteed at industrial temperature range. data retention characteristic is for l-ver only. parameter symbol test condition min. typ. max. unit v cc for data retention v dr cs 3 v cc - 0.2v 2.0 - 3.6 v data retention current i dr v cc =3.0v, cs 3 v cc - 0.2v v in 3 v cc - 0.2v or v in 0.2v - - 1.0 ma v cc =2.0v, cs 3 v cc - 0.2v v in 3 v cc - 0.2v or v in 0.2v - - 0.7 data retention set-up time t sdr see data retention wave form(below) 0 - - ns recovery time t rdr 5 - - ms data retention wave form cs controlled v cc 3.0v v ih v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 10 september 2001 #1 44-soj-400 #44 25.58 0.12 1.125 0.005 max 28.98 1.141 max 0.148 3.76 1.19 ( ) 0.047 1.27 ( ) 0.050 0.95 ( ) 0.0375 + 0.10 0.43 - 0.05 + 0.004 0.017 - 0.002 + 0.10 0.71 - 0.05 + 0.004 0.028 - 0.002 1.27 0.050 1 0 . 1 6 0 . 4 0 0 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 9.40 0.25 0.370 0.010 min 0.69 0.027 #22 #23 0.004 0.10 max 11.18 0.12 0.440 0.005 package dimensions units:millimeters/inches 1.00 0.10 0.039 0.004 44-tsop2-400bf 0.002 #1 0.05 #22 #23 0.30 0.012 0.80 0.0315 min 0.047 1.20 max 0.741 18.81 max 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0.075 - 0.035 0.50 + 0.003 - 0.001 0.125 0.005 0.020 1 0 . 1 6 0 . 4 0 0 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 ( ) 0.805 0.032 ( ) max units:millimeters/inches #44 0.25 0.010 typ + 0.10 - 0.05 + 0.004 - 0.002
K6R4016V1C-c/c-l, K6R4016V1C-i/c-p cmos sram prelimpreliminarypppppppppinary rev 5.0 - 11 september 2001 c 1 / 2 package dimensions units : millimeter. 6 5 4 3 2 1 a b c d e f g h c b/2 b c 1 b c bottom view top view d e 2 e 1 e c side view 0 . 8 0 / t y p . 0 . 2 5 / t y p . a y detail a min typ max a - 0.75 - b 8.90 9.00 9.10 b1 - 3.75 - c 8.90 9.00 9.10 c1 - 5.25 - d 0.30 0.35 0.40 e - 1.05 1.20 e1 - 0.80 - e2 0.20 0.25 0.30 y - - 0.08 0.50 0.50 b1 #a1 0 . 3 0 a1 index mark notes. 1. bump counts: 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity: 0.08(max)

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